PRIME Lab
Areas
5
Active
4
In development
1
Join us

Research

We develop hardware for post-quantum cryptography (PQC) and fully homomorphic encryption (FHE). PQC is designed to resist quantum attacks. FHE allows computation on encrypted data. We aim to improve performance and protect these implementations from information leakage. The five areas below explain our work.

Active

Privacy

Computing with encrypted data.

How can a server or wearable device process health data without decrypting it?

We design hardware to make FHE faster and reduce its resource needs. Our work includes CKKS, an FHE scheme for approximate arithmetic. Applications include artificial intelligence (AI) that protects private data and health monitoring with wearable devices.

  • CKKS and approximate arithmetic
  • FHE accelerators
  • Privacy-preserving AI
  • Wearable health data

Representative papers

In development

Resilience

Protecting hardware against information leakage.

Can an accelerator reveal secret keys through its power use or electromagnetic (EM) emissions?

A cryptographic algorithm can be secure in theory while its hardware implementation reveals sensitive information. These leaks are called side channels. We are building a setup to measure power use and EM emissions from PQC accelerators. Our goal is to evaluate attacks and develop defenses, such as masking and hiding, that balance security, speed, and circuit area.

  • Power and EM side-channel analysis
  • Hardware masking and hiding
  • Leakage assessment
  • Fault resilience

Status

This is a new research direction for the lab. We are setting up equipment to measure power use and EM emissions from our accelerators. Our first PhD student can help develop this research.

Active

Integrity

Hardware for digital signatures.

How can hardware make post-quantum signatures fast and practical?

Digital signatures help verify who signed data and whether it has changed. Post-quantum signature schemes are designed to remain secure against quantum attacks. We build accelerators for schemes such as SLH-DSA and Falcon, which require many hashing and arithmetic operations. We also study hardware that provides a trusted foundation for a system.

  • SLH-DSA and XMSS trees
  • Falcon
  • Hash-based signatures
  • Hardware roots of trust

Representative papers

Active

Microelectronics

Arithmetic and circuit design for cryptography.

How small, fast, and energy-efficient can a polynomial multiplier be?

We design circuits for polynomial and large-integer multiplication, which are central to many cryptographic algorithms. Our methods include systolic arrays, Karatsuba multiplication, and Toeplitz matrix-vector product (TMVP) decompositions. We implement these designs on field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Our designs serve both data centers and small Internet of Things (IoT) devices with limited power and chip area.

  • Computer arithmetic
  • Systolic architectures
  • FPGA and ASIC design
  • Very-large-scale integration (VLSI)
  • Area, speed, and energy trade-offs

Representative papers

Active

Encryption

Hardware for post-quantum key exchange.

How can we make post-quantum key exchange fast and efficient?

PQC aims to protect data from attacks by future quantum computers. We design hardware for lattice-based schemes, including Ring-LWE, Ring-Binary-LWE, and LWR/Saber, and for the code-based scheme HQC. Our designs include small cores for devices with limited resources and shared architectures that support several schemes at high speed.

  • Lattice-based key encapsulation mechanisms (KEMs)
  • Ring-Binary-LWE
  • Code-based schemes such as HQC
  • PQC for small devices

Representative papers

Lab equipment

We are setting up the lab in 2026–27. Planned resources include:

  • FPGADevelopment platforms for building and testing prototype accelerators
  • ServersComputing resources for hardware design, simulation, encrypted computation, and machine learning
  • Design toolsElectronic design automation (EDA) tools for FPGA and ASIC design, from hardware descriptions to circuit layout
  • MeasurementsEquipment to record and analyze power use and EM emissions